RT9594A/b 1 ds9594a/b-02 april 2011 www.richtek.com pin configurations ordering information (top view) wqfn-16l 3x3 mosfet integrated smart photoflash capacitor charger with igbt driver features z z z z z 50v mosfet integrated z z z z z 1.6v to 9v battery input voltage range z z z z z two charge current levels setting z z z z z charges any size photoflash capacitor z z z z z adjustable input current z z z z z adjustable output voltage z z z z z charge complete indicator z z z z z built-in igbt driver for igbt application z z z z z constant peak current control z z z z z 16-lead wqfn package z z z z z rohs compliant and halogen free general description the RT9594A/b are complete photoflash module solutions for digital and film cameras. they are targeted for applications that use 2 to 4 aa batteries or 1 to 2 lithium- ion batteries. the RT9594A/b adopt flyback topology which use constant primary peak current and zero secondary valley current to charge photoflash capacitor quickly and efficiently. the built-in 50v mosfet allows flexibility in transformer design and simplifies the pcb layout. the RT9594A/b also integrate an igbt driver for igniting photoflash tube. only a few external components are required, which greatly reduces the pcb space and cost. the RT9594A/b are available in the wqfn-16l 3x3 package. note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. applications z digital still camera z film camera flash unit z camera phone flash vbat vdd 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 fbvd vdout cs agnd stat fb drvout charge drvin vdrv sw pgnd pgnd sw pgnd 17 RT9594A/b package type qw : wqfn-16l 3x3 (w-type) lead plating system g : green (halogen free and pb free) vdd : 5v (typ.) vdd : 3.3v (typ.)
RT9594A/b 2 ds9594a/b-02 april 2011 www.richtek.com typical application circuit note * : if the spike voltage on sw pin is higher than 50v (internal n-mosfet dc rating ) while internal n-mosfet switches off, place the capacitor (c d ) between sw pin and pgnd to reduce the spike voltage. c d 330pf * optional drvin vdrv agnd fb drvout charge cs stat vdd vbat sw fbvd RT9594A/b pgnd 1 : n 8 7 9 6 2 11 15, 16 13, 14 1 10 12 vdout 3 5 4 strobe r3 c out + 100uf/ 330v r1 1k r2 150k 150k v out 3.3v/5v 0.1uf gsd2004s igbt gate r4 1uf 100k c1 v bat 47uf 27k 3.3v/5v r5 c2 c3 drvin vdrv agnd fb drvout charge cs stat vdd vbat sw fbvd RT9594A/b pgnd 1 : n 8 7 9 6 2 11 15, 16 13, 14 1 10 12 vdout 3 5 4 strobe r3 c out + 100uf/ 330v r1 1k r2 150k 150k v out 3.3v/5v 0.1uf gsd2004s igbt gate r4 1uf 100k c1 v bat 47uf 27k 3.3v/5v r5 c2 c3 figure 1. typical application circuit figure 2. application circuit for the gate drive voltage of igbt same as vdd voltage
RT9594A/b 3 ds9594a/b-02 april 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1 vbat battery voltage pin. 2 cs input current setting pin. 3 vdout voltage detector output pin. open drain output. 4 fbvd voltage detector feedback pin. 5 charge charge enable pin. the charge function is executed when charge pin is set from low to high. the chip is in shutdown mode when charge pin is set to low. 6 drvin igbt driver input pin. 7 vdrv igbt driver power pin. 8 drvout igbt driver output pin. 9 agnd analog ground. 10 stat charge status output. open drain output. when target output voltage is reached, n-mosfet turns on. this pin needs a pull up resistor. 11 fb feedback voltage pin. 12 vdd power input pin. 13, 14 sw n-mosfet switching node. 15, 16, 17 (exposed pad) pgnd power ground. the exposed pad must be soldered to a large pcb and connected to pgnd for maximum power dissipation. ipeak ocp maximum off enable vbat fbvd stat cs pgnd sw vdd charge sq r + - 0.8v vdout + - 1v + - 1v fb otp agnd vdrv drvout drvin sw sense
RT9594A/b 4 ds9594a/b-02 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v dd ------------------------------------------------------------------------------------------------------ 6v z battery input voltage, v bat ---------------------------------------------------------------------------------------------- 12v z built-in n-channel enhancement mosfet drain-source voltage ----------------------------------------------------------------------------------------------------- 50v sw pulse current (pulse width 1us) ------------------------------------------------------------------------------ 4a sw continuous current ------------------------------------------------------------------------------------------------- 2a cs, vdout, fbvd, charge, drvin, vd rv, drvout, st at, fb ------------------------------------------ 6v z power dissipation, p d @ t a = 25 c wqfn-16l 3x3 ------------------------------------------------------------------------------------------------------------ 1.67w z package thermal resistance (note 2) wqfn-16l 3x3, ja ------------------------------------------------------------------------------------------------------- 60 c/w wqfn-16l 3x3, jc ------------------------------------------------------------------------------------------------------ 7 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (v dd = 3.3v/5v, t a = 25 c, unless otherwise specification) to be continued parameter symbol test conditions min typ max units v dd operating voltage RT9594A v dd 3.15 3.3 3.4 v rt9594b 4.5 5 5.5 battery voltage v bat 1.6 -- 9 v switch-off current (i vdd ) i vdd _ sw _ off v fb = 1.1v -- 1 10 ua shutdown current (i vdd ) i off charge pin = 0v -- 0.01 1 ua fb voltage v fb 0.985 1 1.015 v line regulation RT9594A v fb 3.15v v dd 3.4v -- -- 8 mv rt9594b 4.5v v dd 5.5v stat open drain r ds(on) -- 11 19 charge enable high v ceh 1.3 -- -- v charge enable low v cel -- -- 0.4 v recommended operating conditions (note 4) z built-in n-channel enhancement mosfet drain-source voltage ----------------------------------------------------------------------------------------------------- 40v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT9594A/b 5 ds9594a/b-02 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a low effective thermal conductivity test board (single layer, 1s) of jedec 51-3 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max units built-in n-channel enhancement mosfet drain-source on-resistance rt 9 594a r ds(on ) i d = 1 0ma -- 300 400 m rt 9 594b -- 250 350 max off time during pre-c harge -- 9 -- us min off time -- 400 -- ns igbt driver igbt driver supply voltage v vdrv 2 -- 5.5 v drvin trip point 0.8 1.5 2.4 v drvout on r esistance to v vdrv v vdrv = 3.3v -- 6 -- drvout on r esistance to gn d v vdrv = 3.3v -- 6 -- propagation delay (r ising) -- 20 -- ns propagation delay (falling) -- 200 -- ns voltage detector voltage d etector trip (falling) v fbvd fbvd falling 0.95 0.99 1.03 v voltage d etector h ysteresis v fbvd_hys -- 65 -- mv vdou t on resistance to gnd -- 12 --
RT9594A/b 6 ds9594a/b-02 april 2011 www.richtek.com typical operating characteristics charging time (1s/div) v out (50v/div) i in (200ma/div) v bat = 3.7v, v dd = 3.3v c out = 140 f charge (5v/div) stat (5v/div) switching time (1 s/div) i pri (1a/div) v sw (20v/div) v out = 300v i sec (200ma/div) switching time (1 s/div) i pri (1a/div) v sw (20v/div) v out = 100v i sec (200ma/div) output voltage vs. v bat 296 298 300 302 304 306 308 1.52.53.54.55.56.5 v bat (v) output voltage (v) t a = 25 c t a = 85 c t a = -40 c charge time vs. v bat 2 3 4 5 6 7 8 9 10 11 12 1234567 v bat (v) charge time (s) v dd = 5v, c out = 140 f v out = 0 to 300v i pk-pri = 1.4a i pk-pri = 1.6a charge time vs. v bat 2 3 4 5 6 7 8 9 10 11 12 1234567 v bat (v) charge time (s) v dd = 3.3v, c out = 140 f v out = 0 to 300v i pk-pri = 1.4a i pk-pri = 1.6a
RT9594A/b 7 ds9594a/b-02 april 2011 www.richtek.com application information the RT9594A/b integrate a constant peak current controller for charging photoflash capacitor and an igbt driver for igniting flash tube. the photoflash capacitor charger uses constant primary peak current and sw falling control to efficiently charge the photoflash capacitor. pulling the charge pin high will initiate the charging cycle. during mos on period, the primary current ramps up linearly according to v bat and primary inductance. a resistor connecting from cs pin to gnd determines the primary peak current. during the mos off period, the energy stored in the flyback transformer is boosted to the output capacitor. the secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the voltage drop of the diode). the sw pin monitors the secondary current. when the secondary current drops to 0a, sw voltage falls then mos on period starts again. the charging cycle repeats itself and charges the output capacitor. the output voltage is sensed by a voltage divider connecting to the anode of the rectifying diode. when the output voltage reaches the desired voltage set by the resistor divider, the charging block will be disabled and stop charging. then stat pin will be pulled low to indicate the complete charging. the voltage-sensing path will be cut off when charging completed to minimize the output voltage decay. both the charge and stat pins can be easily interfaced to a microprocessor in a digital system. transformer the flyback transformer should be appropriately designed to ensure effective and efficient operation. 1. turns ratio the turns ratio of transformer (n) should be high enough so that the absolute maximum voltage rating for the internal n-mosfet drain to source voltage is not exceeded. choose the minimum turns ratio according to the following formula : out min bat v n 45 v ? where : v out : target output voltage v bat : battery voltage 2. primary inductance for each switching cycle, energy transferred to the output capacitor is proportional to the primary inductance for a constant primary current. the higher the primary inductance is, the higher the charging efficiency will be. besides, to ensure enough off time for output voltage sensing, the primary inductance should be high enough according to the following formula : 9 out pri pk pri 400 10 v l ni ? ? v out : target output voltage n : transformer turns ratio i pk-pri : primary peak current 3. leakage inductance the leakage inductance of the transformer results in the first spike voltage w hen n-mosfet turns off. the spike voltage is proportional to the leakage inductance and inductor peak current. the spike voltage must not exceed the dynamic rating of the n-mosfet drain to source voltage (50v). 4. transformer secondary capacitance any capacitance on the secondary can severely affect the efficiency. a small secondary capacitance is multiplied by n 2 when reflected to the primary will become large. this capacitance forms a resonant circuit with the primary leakage inductance of the transformer. therefore, both the primary leakage inductance and secondary side capacitance should be minimized. rectifying diode the rectifying diode should be with short reverse recovery time (small parasitic capacitance). large parasitic capacitance increases switching loss and lowers charging efficiency. in addition, the peak reverse voltage and peak current of the diode should be sufficient. the peak reverse voltage of the diode is approximately : the peak current of the diode equal primary peak current divide transformer turn ratio as the following equation : pk pri pk sec i i n ? ? = pk r bat out (n ) vv v ? + where : n is transformer turns ratio.
RT9594A/b 8 ds9594a/b-02 april 2011 www.richtek.com adjustable input current the RT9594A/b simply adjust peak primary current by a resistor r cs connecting to cs pin as shown in function block diagram. r cs determines the peak current of primary n-mosfet according to the following equation : where the i pk-pri is the primary peak current. users could select appropriate r cs according to the battery capability and required charging time. adjustable output voltage the RT9594A/b sense output voltage by a voltage divider connecting to the anode of the rectifying diode during off time as shown in figure 3. this eliminates power loss at voltage-sensing circuit when charging completed. r1 to r2 ratio determines the output voltage as shown in the typical application circuit. the feedback reference voltage is 1v. if v out = 300v, according the following equation : () fb out r1 r2 r1 r2 vv1 , so 299. r3 r3 ++ =+ = it is recommend to set r3 = 1k and r1 = r2 = 150k for reducing parasitic capacitance coupling effect of the fb pin. r1 and r2 must be greater than 0805 size resistor for enduring secondary hv. another sensing method is to sense the output voltage directly as shown in figure 4. figure 5. two stage charging application circuit cs pk pri 40000 r () i ? = figure 3. sensing anode of diode figure 4. sensing output voltage r3 c out r1 66.5k r2 10m 10m v out fb c1 10nf r3 c out r1 1k r2 150k 150k v out fb lower charging current at low battery voltage the RT9594A/b also offers two stage charging function. if the resistor divider is connected from v bat to fbvd to gnd as shown in figure 5, it will detect the battery voltage. because of the reference voltage of the internal detector is 1v, thus the battery trip point is 2.5v. when battery voltage is >2.5v, the vdout open drain mos inside the RT9594A/b will be turned on (vdout state become gnd), the peak current value will be determined by r4. when battery voltage is <2.5v, the vdout open drain mos inside the RT9594A/b will be turned off (vdout state become open), then the peak current is determined by r4 series with r5. thus charging current is decreasing as shown in figure 7. as shown in the figure 6 circuit, the fbvd voltage also could be set by the gpio signal. when gpio voltage is >1v, the first stage peak current value will be determined by r4. when the gpio voltage is <1v, the second stage peak current is determined by r4 series with r5. vdd stat charge drvin vdrv drvout agnd fb cs sw vbat pgnd fbvd vdout RT9594A/b r1 150k r2 150k r3 1k strobe 100k 1uf 0.1uf 47uf v bat 3.3v 3.3v/5v v out c out 100uf /330v to igbt gate 1:n gsd2004s r4 24k r5 3k r6 1.5m r7 1m figure 6. two stage charging by gpio signal vdd stat charge drvin vdrv drvout agnd fb cs sw vbat pgnd fbvd vdout RT9594A/b r1 150k r2 150k r3 1k strobe 100k 1uf 0.1uf 47uf v bat 3.3v 3.3v/5v v out c out 100uf /330v to igbt gate 1:n gsd2004s r4 24k r5 3k gpio
RT9594A/b 9 ds9594a/b-02 april 2011 www.richtek.com figure 7. lower charging current time (1s/div) v out (50v/div) i in (200ma/div) v bat < 2.5v v bat (1v/div) change to lower current layout guide for best performance, careful pcb layout is necessary. the following guidelines should be strictly followed when designing a pcb layout for the RT9594A/b. 1. both of primary and secondary power paths should be as short as possible. 2. place the r cs as close to chip as possible. the gnd side of r cs should be directly connected to ground plane to avoid noise coupling. 3. keep fb node area small and far away from nodes with voltage switching to reduce parasitic capacitance coupling effect. 4. the pgnd should be connected to v bat ground plane to reduce switching noise. figure 8. suggestion layout vbat vdd 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 fbvd vdout cs agnd stat fb drvout charge drvin vdrv sw pgnd pgnd sw pgnd 17 agnd pgnd pgnd v out v bat bottom
RT9594A/b 10 ds9594a/b-02 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
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